Cadence: Virtuoso Platform with advanced node support down to 5nm

Cadence Design Systems introduced major enhancements to its Cadence Virtuoso custom IC design platform that improve electronic system and IC design productivity. The enhancements affect almost every Virtuoso product, providing system engineers with a robust environment and ecosystem to design, implement and analyze complex chips, packages, boards and systems.

The updated Virtuoso System Design Platform now allows system engineers to seamlessly edit and analyze the most complex heterogeneous systems. It enables package, photonics, IC analog and RF engineers to work through a single platform and utilize the full breadth of the Virtuoso platform’s most trusted set of design applications. In the heart of the new system design environment is a set of technologies that enable simultaneous edits across multiple process design kits and technologies. The platform also provides seamless interoperability with Cadence SiP Layout and the Sigrity analysis technology portfolio for a comprehensive chip-to-board toolset.

In this release of the Virtuoso platform, Cadence incorporated innovative advanced-node methodologies that speed the designs done in process technologies from 22nm down to 5nm. By collaborating with leading-edge foundries, ecosystem partners and customers, Cadence developed advanced technologies that automatically manage process complexities with innovative methodologies that allow engineers to focus on their design intent. In circuit design and analysis, advanced statistical algorithms specifically targeting FinFET designs uncover circuit variances early, reducing design variation analysis time by approximately 20% using advanced statistical algorithms.

In layout design, a unique multi-grid system abstracts complex design rules of the latest 7nm and 5nm processes, while allowing engineers to increase their use of placement and routing technologies to significantly increase layout design productivity. Using these techniques with the enhancements made to the advanced methodology reduces layout effort by >3X in 7nm production designs.

Cadence made several enhancements to improve analog design and analysis. The Virtuoso Analog Design Environment simulation throughput is improved by up to 3x due to enhanced integration with the Cadence Spectre Circuit Simulator, increasing simulation throughput and using advanced analysis to reduce design iterations. Unique capabilities were added to the Virtuoso ADE Verifier to centralize cross-domain electrical specifications so the path to standards compliance (e.g., ISO 26262) is streamlined by approximately 30 percent.

The Virtuoso Layout environment is evolving from an electrically aware layout to the industry’s first electrically and simulation-driven layout using unique sets of in-design technologies to ensure circuit integrity and performance. This new simulation-driven layout addresses many of the electromigration and parasitic challenges of critical circuits and advanced-node designs. To increase layout automation, the new environment introduces breakthrough techniques for hierarchical floorplanning and planning along with new placement and routing automation technologies to increase layout design productivity and throughput and to shorten layout turnaround time.

With the complexity of today’s chips, one of the big challenges is dividing layout tasks among the design team. The Virtuoso platform now features an innovative concurrent real-time team design editing capability, allowing teams to distribute layout tasks and perform what-if explorations. This is particularly useful for design-rule check fixing, chip finishing and manual routing.

Cadence estimates that the new innovative layout environment with electrically driven routing and wire editing, real-time design editing and revolutionary design planning techniques improves productivity by up to 50 percent.

More Information...

Latest News from Cadence Design Systems

Cadence: connect, share, and inspire at CDNLive EMEA 2018 user conference
Cadence: 5th gen Vision Q6 DSP targets smartphone, surveillance, automotive, AR/VR
Cadence: Virtuoso Platform with advanced node support down to 5nm
Cadence: Sigrity PowerDC supports open neutral file format for thermal interoperability
Cadence announces PCI Express 5.0 Verification IP with TripleCheck technology
Cadence: Xcelium logic simulation technology for Arm-based servers
Cadence achieves “Fit for Purpose - TCL1” certification in support of ISO 26262 standard
Cadence: Genus synthesis solution improves multi-functional printer SoCs design development
Cadence: tool suites optimized for Arm Cortex-A75 and Cortex-A55 CPUs and Mali-G72 GPU

Grammatech talks about the importance of software in engineering

In this video Mark Hermeling of Grammatech talks to Alix Paultre after the Embedded World show in Nuremberg about the importance of software verification for security and safety in electronic design. ...


Lattice Semi walks through their booth demos at Embedded World

In this video Lattice Semiconductor walks us through their booth demonstrations at Embedded World 2018. The live demonstrations include an operating IoT remote vehicle, a low-power network used for vi...


Maxim describes their latest security solution at Embedded World 2018

In this video Scott from Maxim Integrated describes their latest security solution at Embedded World 2018. In the live demo he shows the DS28E38 DeepCover Secure ECDSA Authenticator, an ECDSA public k...


Garz & Fricke at Embedded World 2018 - Embedded HMIs and SBCs “Made in Germany”

You are looking for a HMI-system or single components as touches, displays and ARM-based SBCs? Welcome at Garz & Fricke – the Embedded HMI Company! Our offering ranges from typical single co...


ECRIN Systems myOPALE: Remote Embedded Modular Computers

myOPALE™ offers disruptive technology to multiply capabilities of your next Embedded Computers in a smaller foot print thanks to PCI Express® over Cable interconnect, standard 5.25’&rs...


TechNexion rolls out embedded systems, modules, Android Things kits at Embedded World 2018

In this video John Weber of TechNexion talks to Alix Paultre about how the company helps its customers getting products to market faster. By choosing to work with TechNexion, developers can take advan...


Mike Barr talks cybersecurity

In this video Mike Barr, CEO of the Barr Group, talks to Alix Paultre about cybersecurity at the Embedded World conference in Nuremberg, Germany. Too many designers, even in critical spaces like milit...


Ted Marena of Microsemi talks about their scope-free on-chip debug tools

In this video Ted Marena of Microsemi talks about their scope-free on-chip debug tools with Alix Paultre at Embedded World 2018. SmartDebug tool works with the Microsemi FPGA array and SERDES without ...


Infineon demonstrates their iMotion motor control solution at Embedded World

In this video Infineon explains their latest  IMC100 series iMOTION motor control IC at Embedded World 2018 in Nuremberg. The device provides a ready-to-use solution for high-efficiency variable-...


Samsung goes over their new ARTIK IoT development system

In this video James Stansberry of Samsung talks to Alix Paultre about their ARTIK IoT development system at Embedded World in Nuremberg. The family of system-on-modules provide a complete, production-...


Cypress explains their latest low-power 32-bit Arm Cortex-M4 PSoC 6

In this video Allen Hawes of Cypress Semiconductor talks to Alix Paultre about their latest low-power 32-bit Arm Cortex-M4 PSoC 6, designed to provide a secure high-performance MCU for next-generation...


wholesale jerseys