Curtiss-Wright Controls Defense Solutions

Homepage: www.cwcdefense.com

Company Profile




Curtiss-Wright debuts RACE++ support on CHAMP-AV5 VME DSP engine

Curtiss-Wright Controls Defense Solutions announces that its dual Intel Core i7-based CHAMP-AV5 DSP VME engine now supports RACE++ fabric communications with Eclipse’s MEM1600 RACE++ XMC mezzanine modules. With support for RACE++, the CHAMP-AV5 can now be used to upgrade legacy systems designed with older processor technology without requiring replacement of existing backplanes and enclosures. This enables system designers to significantly improve the performance of older systems quickly and cost-effectively. For example, the CHAMP-AV5 can be used to upgrade a legacy Radio Tuner system originally based on a competitor’s legacy module. Eclipse’s MEM1600 RACE++ XMC card, installed on the CHAMP-AV5, can communicate with incumbent Eclipse Radio Tuner cards already integrated into such a system, resulting in increased overall system performance

The CHAMP-AV5 multi-processing board brings the floating-point performance of the Intel Intel Core i7-610E processor to the VME64x form factor standard. Utilizing a pair of 2.53 GHz dual-core Intel Core i7-610E processors, the CHAMP-AV5 delivers performance rated up to 81 GFLOPS. With a 17GB/s (peak) DDR3 memory subsystem connected directly to the processor, the Core i7 is able to maximize the throughput of its SSE 4.2 vector processing units. With more cache than any previous Intel processor, the Core i7 can process larger vectors at peak rates significantly greater than was possible with previous AltiVec-based systems. The CHAMP-AV5 utilizes a pair of 2.53GHz dual-core Core i7 processors in a VME64x form factor standard. The processors are connected using the IDT 89HPES32NT8BG2, a 32-lane, 8-port PCI Express Gen 2 switch designed to support multiprocessor designs through unique features including dual Direct Memory Access functions, multiple clock domain isolation, and an unprecedented eight non-transparent bridging functions to enable root complex isolation, failover support, and inter-processor communication between PCIe domains.

The CHAMP-AV5 is pin-compatible with the Curtiss-Wright Controls’ MPC7447/7448-based CHAMP-AV4, which enables performance upgrades without the requiring changing the chassis, backplane, or power supplies of existing qualified systems. The CHAMP-AV5 features a high-bandwidth PCI Express architecture, with on-board PCIe connections between the processors and the PMC/XMC sites. With 8GB of Flash and 4GB of SDRAM, the CHAMP-AV5 is designed for applications with demanding storage, data logging and sensor processing requirements. The Eclipse PMC/XMC Memory Module is a 16 GB SDRAM buffer with 64-bit PCI, PCIe x4, and slave RACEway interfaces on a single PMC card. An Altera Stratix IV FPGA controls the flow of data to and from the SDRAM. The card can be operated in three different modes: PCI/RACE; PCIe/RACE; and PCIe-only. Remote field upgrade of the FPGA firmware is supported.

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