BittWare releases the S5-PCIe, a PCIe x8 card based on Altera’s high-performance Stratix V FPGA providing two VITA-57 FMC sites for additional I/O and processing, and two optional QSFP+ cages for serial I/O. When combined with BittWare’s value-added products for FPGA – the Anemone FPGA co-processor and the ATLANTiS FrameWork for FPGA integration and development – the S5-PCIe creates a flexible and efficient solution for high-performance signal processing and data acquisition. The S5-PCIe board features either an Altera Stratix V GX FPGA or a Stratix V GS FPGA, which offers additional DSP resources, and up to 32 GB of DDRs SDRAM. By providing a direct path to the high-performance Stratix V FPGA, the S5-PCIe enables customers to go-to-market with a Stratix V FPGA-based solution quickly and efficiently.
Designed for high-end applications, the Stratix V FPGA provides a high level of system integration and flexibility for I/O, routing and processing. It is optionally supported by BittWare’s Anemone chip – the low power, floating point, c-programmable FPGA co-processor, and the ATLANTiS FrameWork, which is implemented in the FPGA and greatly simplifies application development and integration. The board provides up to 32 GB ofDDR3 SDRAM with error-correcting code. Providing additional flexibility are up to two VITA 57-FMC sites for enhancing the boards I/O and processing capabilities. The board also has the option of two front-panel QSFP+ cages for serial I/O.
Stratix V GX and Stratix V GS FPGAs are optimized for high-performance, high-bandwidth applications with integrated 14.1 Gbps transceivers supporting backplanes and optical modules. The devices support 1.6 Tbps of serial switching capability, 2.5 TMACS of signal-processing performance, and 6 x 72 DDR3 memory interfaces at 1,066 MHz. The Stratix V also provides PCI Express Gen3 x8 via a hard IP block and supports configuration by PCI Express using the existing PCI Express link in your application. The FPGA implements BittWare’s ATLANTiS FrameWork and provides seamless routing of all on-board data, I/O, and memory. The S5PE features up to two FMC sites, which provide high-performance SerDes and LVDS, along with clocks, I2C, JTAG and reset connected to the Stratix V FPGA. The sites are based on the VITA 57 mezzanine standard for FPGA I/O, enabling designers to customise the S5PE to their individual needs with optional FMC I/O boards.
In addition to the FMC I/O, the S5PE provides a variety of interfaces for high-speed serial I/O as well as debug support. Two QSFP+ cages are optional available on the front panel providing support for virtually any serial communication standard, including: Fibre Channel, 40 GigE, 10 GigE, SONET, CPRI, OBSAI, Serial RapidIO, and SerialLite. The eight QSFP+ SerDes channels are connected directly to the Stratix V FPGA. The x8 PCIe interface provides 8 SerDes lanes to the Stratix V FPGA. USB 2.0, RS-232, and JTAG interfaces are available for debug programming support.
