Evatronix have announced a synthesizable USB High Speed Hub that supports High Speed mode requirements of the USB 3.0 Hub specification, and features an aggressive power management function provided by Link Power Management mode for all supported speed rates. The new generation of the USB High Speed Hub offers single or multiple Transaction Translators and a configurable number of downstream ports (up to 15). For further customization of the hub, all its descriptors can be configured to the designer’s liking. Thanks to its customizable architecture the hub can be provided in three versions: as a bare version with repeater-enhanced UTMI+ outputs, as a digital PHY enabled IP with pre-configured upstream and downstream UTMI PHY digital logic or as a complete, standalone hub targeted for particular technology together with the Evatronix USBHS-PHY.
The Low Power Management feature secures the hub's compatibility with the USB 3.0 specification and thus enables designers to include the hub in the USB 3.0 hub IP as a part responsible for High, Full, and Low Speed transfers. For immediate prototyping, a proprietary board can be delivered with test chip PHYs. With its CPU-less architecture, the design is ready for verification and testing in developer’s environment right out of the box. The previous generation USB 2.0 Hub from Evatronix will be available from now on only for embedded applications as the USBHS-HUB-E, and feature some advanced optimization towards such implementations.
The Evatronix USB IP product suite consists of many varied, but complementary elements essential for a successful USB design. From USB-IF certified IP cores supporting all available speed rates, through integrated software stacks, to proprietary PHYs, Evatronix provides complete solutions for every USB-enabled SoC.
